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We study the impact of tunable parameters on computational intensity (i.e.,inverse code balance) and energy consumption of multicore-optimized wavefrontdiamond temporal blocking (MWD) applied to different stencil-based updateschemes. MWD combines the concepts of diamond tiling and multicore-awarewavefront blocking in order to achieve lower cache size requirements thanstandard single-core wavefront temporal blocking. We analyze the impact of thecache block size on the theoretical and observed code balance, introduce looptiling in the leading dimension to widen the range of applicable diamond sizes,and show performance results on a contemporary Intel CPU. The impact of codebalance on power dissipation on the CPU and in the DRAM is investigated andshows that DRAM power is a decisive factor for energy consumption, which isstrongly influenced by the code balance. Furthermore we show that highestperformance does not necessarily lead to lowest energy even if the clock speedis fixed.

Towards energy efficiency and maximum computational intensity for stencil algorithms using wavefront diamond temporal blocking