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A mathematical characterization of serially-pruned permutations (SPPs)employed in variable-length permuters and their associated fast pruningalgorithms and architectures are proposed. Permuters are used in many signalprocessing systems for shuffling data and in communication systems as anadjunct to coding for error correction. Typically only a small set of discretepermuter lengths are supported. Serial pruning is a simple technique to alterthe length of a permutation to support a wider range of lengths, but results ina serial processing bottleneck. In this paper, parallelizing SPPs is formulatedin terms of recursively computing sums involving integer floor and relatedfunctions using integer operations, in a fashion analogous to evaluatingDedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) ispresented, and closed-form expressions for BRP statistics are derived. It isshown that BRP sequences have weak correlation properties. A new statisticcalled permutation inliers that characterizes the pruning gap of prunedinterleavers is proposed. Using this statistic, a recursive algorithm thatcomputes the minimum inliers count of a pruned BR interleaver (PBRI) inlogarithmic time complexity is presented. This algorithm enables parallelizinga serial PBRI algorithm by any desired parallelism factor by computing thepruning gap in lookahead rather than a serial fashion, resulting in significantreduction in interleaving latency and memory overhead. Extensions to 2-D blockand stream interleavers, as well as applications to pruned fast Fouriertransforms and LTE turbo interleavers, are also presented. Moreover,hardware-efficient architectures for the proposed algorithms are developed.Simulation results demonstrate 3 to 4 orders of magnitude improvement ininterleaving time compared to existing approaches.

Pruned Bit-Reversal Permutations: Mathematical Characterization, Fast Algorithms and Architectures