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As the complexity of the scan algorithm is dependent on the number of designregisters, large SoC scan designs can no longer be verified in RTL simulationunless partitioned into smaller sub-blocks. This paper proposes a methodologyto decrease scan-chain verification time utilizing SCE-MI, a widely usedcommunication protocol for emulation, and an FPGA-based emulation platform. Ahigh-level (SystemC) testbench and FPGA synthesizable hardware transactormodels are developed for the scan-chain ISCAS89 S400 benchmark circuit forhigh-speed communication between the host CPU workstation and the FPGAemulator. The emulation results are compared to other verificationmethodologies (RTL Simulation, Simulation Acceleration, and Transaction-basedemulation), and found to be 82% faster than regular RTL simulation. Inaddition, the emulation runs in the MHz speed range, allowing the incorporationof software applications, drivers, and operating systems, as opposed to the Hzrange in RTL simulation or sub-megahertz range as accomplished intransaction-based emulation. In addition, the integration of scan testing andacceleration/emulation platforms allows more complex DFT methods to bedeveloped and tested on a large scale system, decreasing the time to market forproducts.

Co-Emulation of Scan-Chain Based Designs Utilizing SCE-MI Infrastructure