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The surface detector (SD) array of the Pierre Auger Observatory containing atpresent 1680 water Cherenkov detectors spread over an area of 3000 km^2 startedto operate since 2004. The currently used Front-End Boards are equipped withno-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamicrange).  Huge progress in electronics and new challenges from physics impose asignificant upgrade of the SD electronics either to improve a quality ofmeasurements (much higher sampling and much wider dynamic range) or pick-upfrom a background extremely rare events (new FPGA algorithms based onsophisticated approaches like e.g. spectral triggers or neural networks). Muchhigher SD sensitivity is necessary to confirm or reject hypotheses critical fora modern astrophysics.  The paper presents the Front-End Board (FEB) with the biggest Cyclone V EFPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bitresolution. Considered sampling for the SD is 120 MSps, however, the FEB hasbeen developed with external anti-aliasing filters to keep a maximalflexibility. Six channels are targeted to the SD, two the rest for otherexperiments like: Auger Engineering Radio Array and additional muon counters.  The FEB is an intermediate design pluged-in the actually used Unified Boardcommunicating with micro-controller at 40 MHz, however providing even 250 MSPssampling with 20-bit dynamic range, equipped in a virtual NIOS processor andsupporting 256 MB of SDRAM as well as with an implemented spectral triggerbased on the Discrete Cosine Transform for a detection of very inclined "old"showers. The FEB can also support a neural network developing for a detectionof "young" showers, potentially generated by neutrinos.

Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics