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The main objective of this paper is to present a mechanism of enhanced pagingsupport for the second generation microkernels in the form of explicit supportof multi-pager environment for the tasks running in the system. Proposedmechanism is based on the intra-kernel high granularity pagers assignments pervirtual address space, which allow efficient and simple dispatching of pagefaults to the appropriate pagers. The paging is one of the major features ofthe virtual memory, which is extensively used by advanced operating systems toprovide an illusion of elastic memory. Original and present second generationmicrokernels provide only limited, inflexible and unnatural support for paging.Furthermore, facilities provided by current solutions for multi-pager supporton the runtime level introduce an overhead in terms of mode switches and threadcontext switches which can be significantly reduced. Limited paging supportlimits the attractiveness of the second generation microkernel based systemsuse in real-life applications, in which processes usually have concurrentservicing of multiple paging servers. The purpose of this paper is to present afacilities for the efficient and flexible support of multi-pager environmentsfor the second generation microkernels. A comparison of the proposed solutionto the present architecture L4 + L4Re has been made and overhead of the pagefault handling critical path has been evaluated. Proposed solution is simpleenough and provides a natural and flexible support of multi-pager environmentsfor second generation microkernels in efficient way. It introduces a third lessoverhead in terms of the mode switches and thread context switches incomparison to the present L4 + L4Re solution implemented in the Fiasco.OC.

An Enhanced Multi-Pager Environment Support for Second Generation Microkernels