English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

FIR filters are used in many performance/power critical applications such asmobile communication devices, analogue to digital converters and digital signalprocessing applications. Design of appropriate FIR filters usually causes theorder of filter to be increased. Synthesis and tape-out of high-order FIRfilters with reasonable delay, area and power has become an important challengefor hardware designers. In many cases the complexity of high-order filterscauses the constraints of the total design could not be satisfied. In thispaper, efficient hardware architecture is proposed for distributed arithmetic(DA) based FIR filters. The architecture is based on optimized combination ofLook-up Tables (LUTs) and compressors. The optimized system level solution isobtained from a set of dynamic programming optimization algorithms. Theexperiments show the proposed design educed the delay cost between 16%-62.5% incomparison of previous optimized structures for DA-based architectures.

A Flexible Design for Optimization of Hardware Architecture in Distributed Arithmetic based FIR Filters