English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Zendy Plus

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Zendy Tools

Zendy Open

In this paper we present the development of Acceleratable UVCs from standardUVCs in SystemVerilog and their usage in UVM based Verification Environment ofImage Signal Processing designs to increase run time performance. This papercovers development of Acceleratable UVCs from standard UVCs for internalcontrol and data buses of ST imaging group by partitioning of transaction-levelcomponents and cycle-accurate signal-level components between the softwaresimulator and hardware accelerator respectively. Standard Co-Emulation API:Modeling Interface (SCE-MI) compliant, transaction-level communications linkbetween test benches running on a host system and Emulation machine isestablished. Accelerated Verification IPs are used at UVM based VerificationEnvironment of Image Signal Processing designs both with simulator and emulatoras UVM acceleration is an extension of the standard simulation-only UVM and isfully backward compatible with it. Acceleratable UVCs significantly reducesdevelopment schedule risks while leveraging transaction models used duringsimulation.  In this paper, we discuss our experiences on UVM based methodology adoptionon TestBench-Xpress(TBX) based technology step by step. We are also doingcomparison between the run time performance results from earlier simulator-onlyenvironment and the new, hardware-accelerated environment. Although this paperfocuses on Acceleratable UVCs development and their usage for image signalprocessing designs, Same concept can be extended for non-image signalprocessing designs.  KEYWORDS- SystemVerilog, Universal Verification Methodology (UVM),TestBench-Xpress (TBX), Universal Verification Component (UVC), StandardCo-Emulation API: Modelling Interface (SCE-MI), Acceleratable UVC, Emulator,XRTL Tasks/Functions (xtf), Transactor interface (tif), Verification IP (VIP).

Accelerating SystemVerilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator