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Modern multicore processors are employing large last-level caches, forexample Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOStechnology generation, leakage energy has been dramatically increasing andhence, leakage energy is expected to become a major source of energydissipation, especially in last-level caches (LLCs). The conventional schemesof cache energy saving either aim at saving dynamic energy or are based onproperties specific to first-level caches, and thus these schemes have limitedutility for last-level caches. Further, several other techniques requireoffline profiling or per-application tuning and hence are not suitable forproduct systems. In this research, we propose novel cache leakage energy savingschemes for single-core and multicore systems; desktop, QoS, real-time andserver systems. We propose software-controlled, hardware-assisted techniqueswhich use dynamic cache reconfiguration to configure the cache to the mostenergy efficient configuration while keeping the performance loss bounded. Toprofile and test a large number of potential configurations, we utilizelow-overhead, micro-architecture components, which can be easily integratedinto modern processor chips. We adopt a system-wide approach to save energy toensure that cache reconfiguration does not increase energy consumption of othercomponents of the processor. We have compared our techniques with thestate-of-art techniques and have found that our techniques outperform them intheir energy efficiency. This research has important applications in improvingenergy-efficiency of higher-end embedded, desktop, server processors andmultitasking systems. We have also proposed performance estimation approach forefficient design space exploration and have implemented time-sampling basedsimulation acceleration approach for full-system architectural simulators.

Dynamic cache reconfiguration based techniques for improving cache energy efficiency