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The scaling of high density NOR Flash memory devices with multi level cell(MLC) hits the reliability break wall because of relatively high intrinsic biterror rate (IBER). The chip maker companies offer two solutions to meet theoutput bit error rate (OBER) specification: either partial coverage with errorcorrection code (ECC) or data storage in single level cell (SLC) withsignificant increase of the die cost. The NOR flash memory allows to writeinformation in small portions, therefore the full error protection becomescostly due to high required redundancy, e.g. $\sim$50%. This is very differentfrom the NAND flash memory writing at once large chunks of information; NANDECC requires just $\sim$10% redundancy. This paper gives an analysis of a novelerror protection scheme applicable to NOR storage of one byte. The method doesnot require any redundant cells, but assumes 5th program level. The informationis mapped to states in the 4-dimensional space separated by the minimalManhattan distance equal 2. This code preserves the information capacity: onebyte occupies four memory cells. We demonstrate the OBER $\sim$ IBER$^{3/2}$scaling law, where IBER is calculated for the 4-level MLC memory. As anexample, the 4-level MLC with IBER $\sim10^{-9}$, which is unacceptable forhigh density products, can be converted to OBER $\sim10^{-12}$. We assume thatthe IBER is determined by the exponentially distributed read noise. This is thecase for NOR Flash memory devices, since the exponential tails are typical forthe random telegraph signal (RTS) noise and for most of the charge loss, chargegain, and charge sharing data losses.

Error Correction for NOR Memory Devices with Exponentially Distributed Read Noise