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Most PLL architectures have inherent trade-off between settling time andjitter. This trade-off is ignored by commonly used Figure of Merit (FoM) forPLL, which considers only jitter and power for benchmarking PLL performance.This work proposes new Figure of Merit for PLL, which considers settling timealso as performance parameter, along with jitter and power. In this work,trade-off between settling time and jitter is analyzed inlinear/non-linear/hybrid PLLs, theoretically and with behavioral simulations.Then, based on settling time vs. jitter relation obtained, currently usedFigure of Merit for PLL is modified to consider all important specificationsi.e. lock time, power and jitter.

Trade-off between Settling Time and Jitter in Phase Locked Loop