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Topologically quantum error corrected logical gates are complex. Chains oferrors can form in space and time and diagonally in spacetime. It is highlynontrivial to determine whether a given logical gate is free of low weightcombinations of errors leading to failure. We report a new tool Nestcheckcapable of analyzing an arbitrary topological computation and determining theminimum number of errors required to cause failure.

Checking the error correction strength of arbitrary surface code logical gates