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This report introduces a shared resource arbitration scheme "DPQ - DynamicPriority Queue" which provides bandwidth guarantees and low worst case latencyto each master in an MPSoC. Being a non-trivial candidate for timing analysis,SDRAM has been chosen as a showcase, but the approach is valid for any sharedresource arbitration.  Due to its significant cost, data rate and physical size advantages, SDRAM isa potential candidate for cost sensitive, safety critical and space conservingsystems. The variable access latency is a major drawback of SDRAM that induceslargely over estimated Worst Case Execution Time (WCET) bounds of applications.In this report we present the DPQ together with an algorithm to predict theshared SDRAM's worst case latencies. We use the approach to calculate WCETbounds of six hardware tasks executing on an Altera Cyclone III FPGA withshared DDR2 memory. The results show that the DPQ is a fair arbitration schemeand produces low WCET bounds.

Dynamic Priority Queue: An SDRAM Arbiter With Bounded Access Latencies for Tight WCET Calculation