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In the field of cryptography till date the 1-byte in 1-clock is the bestknown RC4 hardware design [1], while the 1-byte in 3clocks is the best knownimplementation [2,3]. The design algorithm in [1] considers two consecutivebytes together and processes them in 2 clocks. The design of 1-byte in 3-clocksis too much modular and clock hungry. In this paper considering the RC4algorithm, as it is, a simpler RC4 hardware design providing higher throughputis proposed in which 1-byte is processed in 1-clock. In the design twosequential tasks are executed as two independent events during rising andfalling edges of the same clock and the swapping is directly executed using aMUX-DEMUX combination. The power consumed in behavioral and structural designsof RC4 are estimated and a power optimization technique is proposed. The NISTstatistical test suite is run on RC4 key streams in order to know itsrandomness property. The encryption and decryption designs are respectivelyembedded on two FPGA boards with RC4 in a custom coprocessor followed byEthernet communication.

A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication