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Layered decoding is well appreciated in Low-Density Parity-Check (LDPC)decoder implementation since it can achieve effectively high decodingthroughput with low computation complexity. This work, for the first time,addresses low complexity column-layered decoding schemes and VLSI architecturesfor multi-Gb/s applications. At first, the Min-Sum algorithm is incorporatedinto the column-layered decoding. Then algorithmic transformations andjudicious approximations are explored to minimize the overall computationcomplexity. Compared to the original column-layered decoding, the new approachcan reduce the computation complexity in check node processing for high-rateLDPC codes by up to 90% while maintaining the fast convergence speed of layereddecoding. Furthermore, a relaxed pipelining scheme is presented to enable veryhigh clock speed for VLSI implementation. Equipped with these new techniques,an efficient decoder architecture for quasi-cyclic LDPC codes is developed andimplemented with 0.13um CMOS technology. It is shown that a decoding throughputof nearly 4 Gb/s at maximum of 10 iterations can be achieved for a (4096, 3584)LDPC code. Hence, this work has facilitated practical applications ofcolumn-layered decoding and particularly made it very attractive in high-speed,high-rate LDPC decoder implementation.

Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes