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Future complementary metal oxide semiconductor (CMOS) scaling for advancedintegrated circuit (IC) technologies may well depend on "More than Moore" (MtM)approaches using heterogeneous integration of semiconductor-based devices. Inorder to realise this, advanced packaging technologies including System inPackage (SiP), System on Chip (SoC) and 3D Integrated Circuits (3D ICs) are keyenabling technologies. However, these advanced packages are plagued byreliability problems and to date there is no proven or accepted non-destructivemetrology which can simultaneously probe materials properties such as strain,warpage, dislocation generation, etc. in these systems from bare silicon diethrough to a fully encapsulated packaged system. We report herein on thedevelopment of a novel, x-ray diffraction amd analysis technique, which canaddress this major metrology gap, and we demonstrate the non-destructiveproduction of X-Y spatial maps of deformations and strain fields in Si dieinside fully encapsulated integrated circuit packages. The technique, which wecall 3-dimensional surface modelling (3DSM), is used to obtain high resolution(~3 {\mu}m) strain/warpage maps, and quantitative information on the nature andextent of warpage in a demonstration quad no flat lead (QFN) advanced packagerunning from early stage silicon die bonding through to the end of themanufacturing process, i.e. a fully encapsulated and production ready chip.

Three Dimensionial Surface Modelling: A Novel Analysis Technique for  Non-Destructive X-Ray Diffraction Imaging of Semiconductor Die Warpage &  Strain in Fully Encapsulated Integrated Circuits