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A novel design for a low dropout (LDO) voltage regulator is presented anddedicated to power many sections of a typical cellular handset. However, thesebaseband, RF, and audio sections have different requirements that influencewhich LDO is most appropriate. After discussion of the specific requirements,different LDOs are recommended. Also, some LDO design techniques are brieflydiscussed to demonstrate how an LDO may be optimized for a specific level ofperformance. Cellular phone designs require linear regulators with lowdropout,low-noise, high PSRR, low quiescent current (Iq), and low-cost. They need todeliver a stable output and use smallvalue output capacitors. Ideally, onedevice would have all these characteristics and one low-dropout linearregulator (LDO) could be used anywhere in the phone without worry. But inpractice, the various cell phone blocks are best powered by LDOs with differentperformance characteristics. This paper provides a new design methodology tochoosing the right LDO to power each cell phone and especially for the VoltagePhase-Locked loops (VPLLs) blocks. Fabricated in a 0.18 {\mu}m CMOS process,the measured results show the adopted topology achieves a better phase noisethan the conventional saturation current source. and the spread of the currentlimitation (without matching) is 100mA, the VPLLs system demonstrates a phasenoise of 782 nv/sqrtHz at 100-kHz, and 33 nv/sqrtHz at 1 MHz, while quiescentcurrent 33 {\mu}A from a 2.6 V supply voltage.

A 100 mA Low Voltage Linear Regulators for Systems on Chip Applications Using 0.18 {\mu}m CMOS Technology