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I describe the performance of the CRBLASTER computational framework on a350-MHz 49-core Maestro Development Board (MDB). The 49-core Interim Test Chip(ITC) was developed by the U.S. Government and is based on the intellectualproperty of the 64-core TILE64 processor of the Tilera Corporation. The Maestroprocessor is intended for use in the high radiation environments found inspace; the ITC was fabricated using IBM 90-nm CMOS 9SF technology andRadiation-Hardening-by-Design (RHDB) rules. CRBLASTER is a parallel-processingcosmic-ray rejection application based on a simple computational framework thatuses the high-performance computing industry standard Message Passing Interface(MPI) library. CRBLASTER was designed to be used by research scientists toeasily port image-analysis programs based on embarrassingly-parallel algorithmsto a parallel-processing environment such as a multi-node Beowulf cluster ormulti-core processors using MPI. I describe my experience of porting CRBLASTERto the 64-core TILE64 processor, the Maestro simulator, and finally the 49-coreMaestro processor itself. Performance comparisons using the ITC are presentedbetween emulating all floating-point operations in software and doing allfloating point operations with hardware assist from an IEEE-754 compliantAurora FPU (floating point unit) that is attached to each of the 49 cores.Benchmarking of the CRBLASTER computational framework using thememory-intensive L.A.COSMIC cosmic ray rejection algorithm and acomputational-intensive Poisson noise generator reveal subtleties of theMaestro hardware design. Lastly, I describe the importance of using realscientific applications during the testing phase of next-generation computerhardware; complex real-world scientific applications can stress hardware innovel ways that may not necessarily be revealed while executing simpleapplications or unit tests.

Benchmarking CRBLASTER on the 350-MHz 49-core Maestro Development Board