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In a multiprocessor system on chip (MPSoC) IC the processor is one of thehighest heat dissipating devices. The temperature generated in an IC may varywith floor plan of the chip. This paper proposes an integration and thermalanalysis methodology to extract the peak temperature and temperaturedistribution of 2-dimensional and 3-dimensional multiprocessor system-on-chip.As we know the peak temperature of chip increases in 3-dimensional structurescompared to 2-dimensional ones due to the reduced space in intra-layer andinter-layer components. In sub-nanometre scale technologies, it is inevitableto analysis the heat developed in individual chip to extract the temperaturedistribution of the entire chip. With the technology scaling in new generationICs more and more components are integrated to a smaller area. Along with theother parameters threshold voltage is also scaled down which results inexponential increase in leakage current. This has resulted in rise in hotspottemperature value due to increase in leakage power. In this paper, we haveanalysed the temperature developed in an IC with four identical processors at2.4 GHz in different floorplans. The analysis has been done for both 2D and 3Darrangements. In the 3D arrangement, a three layered structure has beenconsidered with two Silicon layers and a thermal interface material (TIM) inbetween them. Based on experimental results the paper proposes a methodology toreduce the peak temperature developed in 2D and 3D integrated circuits .

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs