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For Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC)designs, Cell - Based Design (CBD) is the most prevalent practice as itguarantees a shorter design cycle, minimizes errors and is easier to maintain.In modern ASIC design, standard cell methodology is practiced with sizablelibraries of cells, each containing multiple implementations of the same logicfunctionality, in order to give the designer differing options based on area,speed or power consumption. For such library cells, thorough verification offunctionality and timing is crucial for the overall success of the chip, aseven a small error can prove fatal due to the repeated use of the cell in thedesign. Both formal and simulation based methods are being used in the industryfor cell verification. We propose a method using the latter approach thatgenerates an optimized set of test vectors for verification of sequentialcells, which are guaranteed to give complete Single Input Change transitioncoverage with minimal redundancy. Knowledge of the cell functionality by meansof the State Table is the only prerequisite of this procedure.

Generation of Test Vectors for Sequential Cell Verification