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Based on the ASIC layout level simulation of 7 types of adder structures eachof four different sizes, i.e. a total of 28 adders, we propose expressions forthe width of each of the three regions of the final Carry Propagate Adder (CPA)to be used in parallel multipliers. We also propose the types of adders to beused in each region that would lead to the optimal performance of the hybridfinal adders in parallel multipliers. This work evaluates the completeperformance of the analyzed designs in terms of delay, area, power throughcustom design and layout in 0.18 um CMOS process technology.

Optimal Final Carry Propagate Adder Design for Parallel Multipliers