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We present new computational building blocks based on memristive devices.These blocks, can be used to implement either supervised or unsupervisedlearning modules. This is achieved using a crosspoint architecture which is anefficient array implementation for nanoscale two-terminal memristive devices.Based on these blocks and an experimentally verified SPICE macromodel for thememristor, we demonstrate that firstly, the Spike-Timing-Dependent Plasticity(STDP) can be implemented by a single memristor device and secondly, amemristor-based competitive Hebbian learning through STDP using a $1\times1000$ synaptic network. This is achieved by adjusting the memristor'sconductance values (weights) as a function of the timing difference betweenpresynaptic and postsynaptic spikes. These implementations have a number ofshortcomings due to the memristor's characteristics such as memory decay,highly nonlinear switching behaviour as a function of applied voltage/current,and functional uniformity. These shortcomings can be addressed by utilising amixed gates that can be used in conjunction with the analogue behaviour forbiomimetic computation. The digital implementations in this paper use in-situcomputational capability of the memristor.

Memristor-based Synaptic Networks and Logical Operations Using In-Situ Computing