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Semi-parallel, or folded, VLSI architectures are used whenever hardwareresources need to be saved at design time. Most recent applications that arebased on Projective Geometry (PG) based balanced bipartite graph also fall inthis category. In this paper, we provide a high-level, top-down designmethodology to design optimal semi-parallel architectures for applications,whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applicationshave been found e.g. in error-control coding and matrix computations. Unlikemany other folding schemes, the topology of connections between physicalelements does not change in this methodology. Another advantage is the ease ofimplementation. To lessen the throughput loss due to folding, we alsoincorporate a multi-tier pipelining strategy in the design methodology. Thedesign methodology has been verified by implementing a synthesis tool in C++,which has been verified as well. The tool is publicly available. Further, acomplete decoder was manually protototyped before the synthesis tool design, toverify all the algorithms evolved in this paper, towards various steps ofrefinement. Another specific high-performance design of an LDPC decoder basedon this methodology was worked out in past, and has been patented as well.

A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices