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This paper shows that not every scan cell contributes equally to the powerconsumption during scan based test. The transitions at some scan cells causemore toggles at the internal signal lines of a circuit than the transitions atother scan cells. Hence the transitions at these scan cells have a largerimpact on the power consumption during test application. These scan cells arecalled power sensitive scan cells.A verilog based approach is proposed toidentify a set of power sensitive scan cells. Additional hardware is added tofreeze the outputs of power sensitive scan cells during scan shifting in orderto reduce the shift power consumption.when multiple scan chain is incorporatedalong with freezing the power sensitive scan cell,over all power during testingcan be reduced to a larger extend.

Power Management during Scan Based Sequential Circuit Testing