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The presence of interface states at the MOS interface is a well-known causeof device degradation. This is particularly true for ultra-scaled FinFETgeometries where the presence of a few traps can strongly influence devicebehavior. Typical methods for interface trap density (Dit) measurements are notperformed on ultimate devices, but on custom designed structures. We presentthe first set of methods that allow direct estimation of Dit instate-of-the-art FinFETs, addressing a critical industry need.

Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs