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This article exhibits a particular encoding of logic circuits into a sheafformalism. The central result of this article is that there exists strictlymore information available to a circuit designer in this setting than exists instatic truth tables, but less than exists in event-level simulation. Thisinformation is related to the timing behavior of the logic circuits, andthereby provides a ``bridge'' between static logic analysis and detailedsimulation.

Asynchronous logic circuits and sheaf obstructions