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Large-capacity Content Addressable Memory (CAM) is a key element in a widevariety of applications. The inevitable complexities of scaling MOS transistorsintroduce a major challenge in the realization of such systems. Convergence ofdisparate technologies, which are compatible with CMOS processing, may allowextension of Moore's Law for a few more years. This paper provides a newapproach towards the design and modeling of Memristor (Memory resistor) basedContent Addressable Memory (MCAM) using a combination of memristor MOS devicesto form the core of a memory/compare logic cell that forms the building blockof the CAM architecture. The non-volatile characteristic and the nanoscalegeometry together with compatibility of the memristor with CMOS processingtechnology increases the packing density, provides for new approaches towardspower management through disabling CAM blocks without loss of stored data,reduces power dissipation, and has scope for speed improvement as thetechnology matures.

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines