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Since J. Mitola's work in 1992, Software Defined Radios (SDRs) have beenquite a hot topic in wireless systems research. Though many notableachievements were reported in the field, the scarcity of computational power ongeneral purpose CPUs has always constrained their wide adoption in productionenvironments. If conveniently applied within an SDR context, classical conceptsknown in computer science as space/time tradeoffs can be extremely helpful whentrying to mitigate this problem. Inspired by and building on those concepts,this paper presents a novel SDR implementation technique which we call MemoryAcceleration (MA) that makes extensive use of the memory resources available ona general purpose computing system, in order to accelerate signal computation.MA can provide substantial acceleration factors when applied to conventionalSDRs without reducing their peculiar flexibility. As a practical proof of this,an example of MA applied in the real world to the ETSI DVB-T Viterbi decoder isprovided. Actually MA is shown able to provide, when applied to such Viterbidecoder, an acceleration factor of 10.4x, with no impact on error correctionperformances of the decoder and by making no use of any other typicalperformance enhancement techniques such as low level (Assembler) programming orparallel computation, which though remain compatible with MA. Opportunity forextending the MA approach to the entire radio system, thus implementing what wecall a Memory-Based Software Defined Radio (MB-SDR) is finally considered anddiscussed.

On Memory Accelerated Signal Processing within Software Defined Radios