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The complexity of multimedia applications in terms of intensity ofcomputation and heterogeneity of treated data led the designers to embark themon multiprocessor systems on chip. The complexity of these systems on one handand the expectations of the consumers on the other hand complicate thedesigners job to conceive and supply strong and successful systems in theshortest deadlines. They have to explore the different solutions of the designspace and estimate their performances in order to deduce the solution thatrespects their design constraints. In this context, we propose the modeling ofone of the design space possible solutions: the software to hardware taskmigration. This modeling exploits the synchronous dataflow graphs to take intoaccount the different migration impacts and estimate their performances interms of throughput.

Performance Analysis of Software to Hardware Task Migration in Codesign