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Compact modeling of MOSFETs from a 0.35 micron SOI technology node operatingat 4 K is presented. The Verilog-A language is used to modify device equationsfor BSIM models and more accurately reproduce measured DC behavior, which isnot possible with the standard BSIM model set. The Verilog-A approach alsoallows the embedding of nonlinear length, width and bias effects into BSIMcalculated curves beyond those that can be achieved by the use of differentBSIM parameter sets. Nonlinear dependences are necessary to capture effectsparticular to 4 K behavior, such as current kinks. The 4 K DC behavior isreproduced well by the compact model and the model seamlessly evolves duringsimulation of circuits and systems as the simulator encounters SOI MOSFETs withdifferent lengths and widths. The incorporation of various length/width andbias dependent effects into one Verilog-A / BSIM4 library, therefore, producesone model for all sets of devices for this technology node.

Compact Modeling of 0.35 micron SOI CMOS Technology Node for 4 K DC Operation using Verilog-A