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The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-onchip (SoC) designs. APB is low bandwidth and low performance bus used to affix the peripherals like UART, Keypad, Timer and other segment equipment’s to the bus architecture. The aim of this paper is to design and implement AMBA APB (Advanced Microcontroller Bus Architecture Advanced Peripheral Bus) Bridge with efficient deployment of system resources. Clock is a major concern in designing of any digital sequential system. Clock skew is introduced when the difference is generated between the arrival times of clock signal. One of the approaches to minimize clock skew is ripple counter. The three bit down ripple counter approach used. APB Bridge with clock skew minimization technique is implemented in the paper using Verilog HDL. For the simulation purpose, Vivado Design Suite ISim has been used. For the synthesization purpose and design utilization summary Vivado Integrated Design Environment (IDE)

Design and FPGA Implementation of AMBA APB Bridge with Clock Skew Minimization Technique