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With ever increasing IC complexity and aggressive technology scaling towards cutting edge technologies, the SOC timing closure is becoming a tedious, time consuming and challenging task. Also in advanced technology nodes one has to consider the effect of PVT variation, temperature inversion, noise effect on delay, which is adding more scenarios for STA to cover. In this work, we have proposed an algorithm for simultaneous usage of data path ECO and clock path ECO for efficient timing closure in SOC. The algorithm here tries to fix multiple failing end points through simple clock path optimization, instead of performing data path optimization across multiple paths, thus reducing area and power overhead. The proposed algorithm is tested on multiple industrial designs and found to achieve 30.98% improvement interms of Worst Negative Slack, 63.63% interms of Total Negative Slack, 58.19% interms of Failing End Points. Also the algorithm is physically aware meaning that the placement blockages, congestions are considered while inserting buffers. The algorithm works under Distributed Multi Scenarios Analysis (DMSA) environment and considers the effect of ECO across multiple corners and modes. Keyword: Engineering Change Order ECO, Clock rescheduling / Clock push pull, physically aware, Distributed Multi Scenario Analysis

Simultaneous Data Path and Clock Path Engineering Change Order for Efficient Timing Closure in Complex SOC