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Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation This thesis looks into the design and simulations of 32 bit booth multiplier with high speed carry select adder in 40 nm process technology and effect of temperature on power consumption. Process level simulation has been carried out on Xilinx suite 12.3.1 and Model -sim. For Investigation about Power, X Power Analyser is used which shows variation of power with respect to temperature.

Delay-Power Performance of High Speed Radix 32 Booth Multiplier in 40nm Process Technology