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This paper presents the realization of area efficient architecture using Distributed Arithmetic with Offset Binary Coding (DA-OBC) for implementation of Finite Impulse Response (FIR) Filter. Area complexity in the algorithm of Finite Impulse Response Filter is mainly caused by multipliers. Among the multiplierless techniques of FIR Filter, Distributed Arithmetic is most preferred area efficient technique. In this technique, partial products of filter coefficients are precomputed and stored in Lookup Table (LUT) and the filtering is done by shift and accumulate operations on these partial products. However, the scale of the LUT will increase exponentially with the co-efficient. If the co-efficient is small, it is very convenient to realize. While the coefficient is large, it will take up a lot of storage resources of FPGA and reduce the calculation speed. The paper presents the improvement of the DA algorithm by reducing the LUT size and delay using Offset Binary Coding Algorithm. The design based on Altera EP2S15F484C3 Chips is synthesized under the integrated environment of Quartus II 9.1. The result of simulation and test shows that Offset Binary Coding greatly reduces the FPGA hardware resources and the high speed filtering is achieved compared to conventional DA Algorithm.

Area Efficient Implementation of FIR Filter Using Distributed Arithmetic with Offset Binary Coding