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Digital Signal Processing (DSP) has become a very important and dynamic research area. Now-aday’s many integrated circuits are dedicated to DSP functions. Fourier Transform is widely used in industrial applications as well as in scientific research. The performance in terms of throughput of the processor is limited by the multiplication. Therefore the multiplier is optimized to make the input to output delay as short as possible. A new FFT architecture based on distributed arithmetic has been developed and is compared to a previous multiplier based FFT. An efficient implementation of a pipelined Radix-2 2 Single Path Delay Feedback FFT is proposed in this paper. In this, Conventional R-2 2 SDF FFT architecture, complex multiplier and multiplier-less architecture based on distributed arithmetic and parallel prefix adder technique are explained. The advantages, performance and timing of the communication modules after implementation of the proposed technique are then discussed at the end. The comparison clearly indicates that the R-2 2 SDF FFT with the proposed architecture is efficient than the other implementations of its kind.

Design of Efficient Pipelined Radix-2 2 Single Path Delay Feedback FFT