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The design is chosen to accomplish the desired necessity in present work we design high broadband frequency divider. It consumes less power and gives low leakage in CMOS based frequency divider with SVL technique, thereby reducing overall power consumption of the circuit. This paper presents various parameters and shows reduced leakage power (0.45×10 -12 ), Delay (6.26psec) and noise margin (11.53) of the circuit to analyze its performance in 45nm technology with U-SVL and L-SVL technology. The simulation results were done with cadence tool virtuoso environment at room temperature 27oC with various supply voltage (0.7 to 1.2V).

Performance Estimation of SVL technique based ½ frequency divider in 45nm CMOS technology