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The ever increasing demand of digital computing and wireless communication have been driving the semiconductor technology to change with passing days. Modern electronics system integrates more complex component and devices, which result in a very complex electromagnetic field environment Moore’s law has driven the scaling of digital electronic devices, dimensions and performances over the last 40 years. In today’s world, there is demand of devices which are faster, better and having less power consumption. Now we need to better optimize the circuit at available technologies. Interconnection used to connect components on a VLSI chip, chips on a multichip module and to connect multichip modules on a system board. Most of the chips are covered by Interconnects. On-chip interconnects which was considered only as a parasitic load before 1990s became the real performance bottleneck due to its extremely reduced cross section dimension [31]. Today, onchip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, higher power dissipation and limited bandwidth.

Review of Electromagnetic failure, optimization techniques and stress prediction in Interconnect