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This paper concerns the design and implementation of CMOS operational amplifier with current mirror load in 0.18um process to satisfy some specifications such as,: VDD = 1.8V, SR >= 10V/us (CL = 2pF), phase margin 60 0 , f-3dB>= 100kHz (CL = 2pF), a small signal gain A >=1000 V/V, ICMR is (0.7V, 1.1V) and Pdiss<=1mW.And shows DC response, AC response, and transient response. CMOS gates are not particularly effective in detecting and reacting to small signal changes, because of the relatively small transconductance of the MOS device. In order to work properly and to achieve high performance, reduced-swing circuits normally require amplifier circuits, whose task it is to restore the signal to its full swing in a minimum amount of time and with a minimum amount of extra energy consumption.

Fully Differential Op-Amp Is Designed Using The Proposed Compensation Scheme