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In this Paper, we propose a low-power multiplier design methodology which has multiplier-andaccumulator for high speed and by adopting the new Shift and adds implementation approach. This multiplier is designed by equipping the Power Suppression Technique on DA (distributed arithmetic) algorithm. The Shift and adder will avoid the unwanted addition and thus minimize the switching power dissipation, the performance was improved. When the DA algorithm is directly applied in FPGA (field programmable gate array) to realize FIR (finite impulse response) filter, it is easy to achieve the best configuration in the coefficient of FIR filter, the storage resources and the computing speed. The parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large. According to this, the paper provides the detailed analysis and discussion in the algorithm, the memory size and the look up table speed. Also, the corresponding optimization and improvement measures are discussed. The design results of simulation and test show that this method greatly reduces the FPGA hardware resource and the high speed filtering is achieved. The design has a big breakthrough compared to the traditional FPGA realization.

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm