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In the world of Integrated Circuits, Complementary Metal–Oxide–Semiconductor (CMOS) has lost its efficiency during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are difficult to hold back. As a result of such SCE many alternate devices have been studied. Some of the major contestants include Multi Gate Field Effect Transistor (MuGFET) like FinFET, Nano tubes, Nano wires etc. In this work, the basic gates and memory circuits like DRAM are designed in HSPICE software using CMOS structure and FinFET structures are analyzed and their performances like average power, standby power dissipation and leakage power are compared. A 32nm technology FinFET model is used to design DRAM. Keyword: CMOS, Dynamic RAM, FinFET, Memory Cell, and Power Dissipation.

Design of Nanoscale 3-T DRAM using FinFET