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The Design is mainly Intended for HDL Design for Exa Hertz Clock based 2e-1 Exa Bits Per Second (Ebps) PRBS Design for Ultra High Speed Applications/Products the estimation of HIGH Speed in terms of Ebps(Exa Bits Per Second) Data Rate for 2e23-1 Tapped PRBS Design Pattern Sequence. The Exa Bits Per Second Data Baud rate Speed estimated by Synchronization with Exa Hertz Clock (2 50 Clock Cycle Periodic time for 1 Exa Hertz Clock frequency ) The Exa Hertz E.B.P.S 2e 23 -1PRBS is Designed by using LFSR Linear Feed Back Shift Register & XOR Gate with Specific Tapping Points(18 and 23) as per CCITT ITU Standards and this design block Purely Synchronized with Exa Hertz Clock. RTL Design Architecture Implemented by using VHDL &/ Verilog HDL, Programming & Debugging Done by using Spartan III FPGA Kit. Transmission done through this carrier frequency. Propagation Carrier Done either Serially / Parallel lines I/O in FPGA.

HDL Design for Exa Hertz Clock based 2e23-1 Exa Bits Per Second (Ebps) PRBS Design for Ultra High Speed Applications/Products