English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

PARAMETERS such as area, power, and delay of highly complex logic circuits used in the field of digital systems can be appropriately optimized by utilizing AND-XOR based circuits rather than AND-OR based Boolean function [1]-[2]. Besides, XOR-based circuits are well suited for testability [3]-[4] and easily mapped into the Field Programmable Gate Arrays (FPGAs). Minimization of ANDXOR nodes (area count) is possible by sharing the sub-functions/ product terms within the multi-output functions. With the reduction of node count, the signal transitions among the sub-function get reduced. ‘Espresso,’ the two-level AND-OR minimizer was developed to eliminate redundant literals from canonical form using unite function decomposition [5]. Low power approaches are established by searching a suitable input variable polarity for maximum sharing of internal nodes to reduce the switching activity of a Boolean function [6]-[8]. There are several sub-classes of AND-XOR circuit synthesis which are of interest. The most general 2-level AND-XOR form is EXOR Sum-Of-Product (ESOP). Due to its non-canonical nature, ESOPs are very hard for optimization. It is observed that any Boolean function can be represented in modulo-2 AND-XOR based algebraic expressions. These expressions are elaborated with the help of Davio functions [9], and are termed as Reed-Muller (RM) expansions. A Boolean function represented in RM form is unique and canonical in nature, consumes less area, reduces power dissipation, and is in readily testable form [4]-[6], [8]. Depending on application-specific advantages, RM circuits are represented in the Positive Polarity Reed-Muller (PPRM) expansion, Fixed Polarity Reed-Muller (FPRM) expansion and Mixed Polarity Reed-Muller (MPRM) expansion. A thorough search on literature review has shown that optimization of MPRM is superior over the FPRM expansions on circuit performance regarding the area, switching activity (dynamic power) and/or delay [6]-[8], [10]-[11]. A fast minimization algorithm (FMA) using the binary differential evolution (BDE) method to minimize the FPRM product term is proposed in [12]. A comparative study of proposed FMA with the genetic algorithm (GA) and simulated annealing genetic algorithm (SAGA) is also reported. An incompletely specified FPRM (ISFPRM) acquisition algorithm is proposed by He et al. in [13]. The authors proposed a chromosome conversion technique to convert zero polarity ISFPRM to the FPRM for power reduction. A hybrid simulated annealing (SA) and discrete particle swarm optimization (DPSO) based area optimization approach is proposed in [14]. Authors in [8], considered the NSGA-II algorithm to find an optimal polarity for power and area optimization of MPRM network. Authors in [8] proposed a chromosome encoding method based on ternary input polarity and binary don’t care allocation. By exploiting the don’t care condition, authors in [15] proposed a delay optimization approach for MPRM based logic. In [15], the authors minimized the weighted Keywords

An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis