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A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu’s 110-nm CMOS process. ※    (NRF 2010-0023315)  IDEC  . First Author : Department of Electronic and Radio Eng. Kyung Hee University, lotus@khu.ac.kr,  ° Corresponding Author : Department of Electronic and Radio Eng. Kyung Hee University, cwkim@khu.ac.kr,  * Department of Electronic and Radio Eng. Kyung Hee University, here33@khu.ac.kr :KICS2014-05-191, Received May 21, 2014; Revised October 6, 2014; Accepted October 6, 2014 I.        ,                    ,             .               .       The Journal of Korean Institute of Communications and Information Sciences '15-01 Vol.40 No.01 10  1. S    Fig. 1. Block diagram of the Class-S amplifier.  2. E         Fig. 2. Structure of the Class-E amplifier and the voltage and current waveforms at the drain node. .            OFDM  LTE(4G)     PAPR(peak-to-average power ratio)  . PAPR            AB    .             .      PAPR     100%          .             (PWM)   .    (PWM)        -     .           .          ‘1’               .       (Noise Shaping) -                  .    110-nm CMOS    S                 ,      . II. S        1 ,   S    . S       (DSM),    ,   (BPF)    .          (PWM)                .            .          ,      .      E       ,     S        . E       2 .                .                  .     CP  ,                 .                  .               -     .                                   .          -                 (SQNR : Signal To Quantization Noise Ratio))    .  / S     CMOS        11  3.      . Fig. 3. Block diagram of the band-pass delta sigma modulator.  4.        Fig. 4. Transfer function of the band-pass delta sigma modulator.  5.       Fig. 5. Circuit diagram of the double-tailed current sense amplifier and the voltage waveform at the output node.           ,  DAC            .              .              ,           .       3   .         , 1 ()  .           .              .                .        ( 1) .   ∙ ∙ (1)      H(s)      ,           .       (2)         4    . III.   (BPDSM)  (PA)            3   .      .

A CMOS Band-Pass Delta Sigma Modulator and Power Amplifier for Class-S Amplifier Applications