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Due to the limited power supply resources, it is essential that the minimization of algorithmic operation and the reduction of the hardware logical-resources in the design of the satellite transponder. It is also required that the transponder process the signals of various bandwidth efficiently, that is suitble for the SDR-based implementation. This paper proposes a variable rate down sampler which can provide variable bandwidth and data rate for carrier, ranging and sub-band command signals respectively. The proposed down sampler can provide multiple 2 M decimated outputs from a single half band filter with recursive arithmetic architecture, which can minimize the hardware resources as well as the arithmetic operations. The algorithm for hardware implementation as well as the analysis for the passband flatness and aliasing is presented and varified by the FPGA implementation. First Author:   , daesungb@gmail.com,  ° Corresponding Author:   , chkim@ssu.ac.kr,  *  , wglim@kari.re.kr :KICS2013-05-215, :2013 5 23, :2013 5 30, :2013 12 9 I.   -  -                 .         (J-KICS) '13-12 Vol.38A No.12 1080 SNR        (Deep Space)     SNR   Kbps bps    . SDR(Software Defined Radio)                ,            (Down Sampling) ,          (Multiplexer)       .            (Cosm ic Ray)      (Fault Tolerant Sys tem)    TMR(Triple Modular Redundancy) ,            3    ,                .                        .      Zero-Pha se FIR   (HBF)           1/4      , (Resampler)       ,  (1-a)   M HBF         ≤ ≤              ≥ ≥        .     HBF     HBF     (Aliasing)    HBF ( 1-b),     VHDL       Xilinx Virtex5 FPGA    . HBF 1 Baseband Input (Data Rate X) HBF 2 HBF 3 HBF M

A Variable Sample Rate Recursive Arithmetic Half Band Filter for SDR-based Digital Satellite Transponders