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—In modern synchronous digital systems, the clock skew problem becomes one of the bottlenecks in achieving high speed and high performance. Several clock deskewing circuits have been used to reduce clock skew. The synchronous mirror delay (SMD) and the delay-locked loop (DLL) are two typical kinds of them. SMDs have advantages of short locking time and low-power characteristics within a wide compensation range, but coarse deskewing resolution are inherent shortcoming of them. Reversely, DLLs have the high deskewing resolution, but long locking time and high power within a wide compensation range are immanent disadvantages of them. Thus, a novel mixed clock deskewing circuit (MCDC), which is mostly a SMD structure with a DLL technique in support, is presented in this paper. The proposed MCDC takes advantages in the other part and complements its weak points each other. The simulation results show that the MCDC has advantages of high resolution, fast locking and low power. In addition, it has a small area characteristic which is propitious to be integrated into high-performance microprocessors.

MCDC: A Novel Mixed Clock Deskewing Circuit