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This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13µm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.

A 6-bit 2GS/s Low Power Flash ADC