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currents in deep sub-micrometer regimes is becoming a significant contributor to power dissipation in CMOS digital circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Therefore, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power consumption, especially for battery powered and portable low-power applications. In this work we have performed an analysis and circuit level simulation at Deep Sub-Micron stability loss with a small area penalty. The standby leakage power is better in P4, and P3 cells by 59%, and 23% to IP3 cell but at the cost of degraded cells' data retentation and stability. The standby leakage power in IP3 is reduced by 36% and 52% in comparison with 6T and PP cell with improved cell stability and performance. The simulation has been carried out on t ox = 2.

Analysis and Simulation of Subthreshold Leakage Current Reduction in IP3 SRAM Bit-Cell at 45nm CMOS Technology for Multimedia Applications