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There are many methods for improving the efficiency of the power amplifier, one of which is Hybrid EER that we use. In this technique, the signal is divided into two parts. In a path the information in the envelope of the signal is detected and is applied to the drain of the transistor. By this method the voltage of the drain is variable and is related to the amplitude of the input signal. In another path the signal is fed to the RF amplifier. In this paper we introduce EER, ET and HEER techniques and explain the envelope amplifier. Design of the envelope amplifier is very important in the system; since it plays a chief role in the total efficiency. We have designed the power amplifier using the MRF6S27015N MOTOROLA transistor in LDMOS technology and applied HEER to our amplifier. It caused more than 50% of PAE in a wide range of input power.

Design and Simulation of a Wideband Hybrid EnvelopeTracking Power Amplifier Using LDMOS Transistor