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By using the dynamic reconfigurable transceiver in high speed interfacedesign, designer can solve critical technology problems such as ensuring signalintegrity conveniently, with lower error binary rate. In this paper, wedesigned a high speed XAUI (10Gbps Ethernet Attachment Unit Interface) totransparently extend the physical reach of the XGMII. The following points arefocused: (1) IP (Intellectual Property) core usage. Altera Co. offers twotransceiver IP cores in Quartus II MegaWizard Plug-In Manager for XAUI designwhich is featured of dynamic reconfiguration performance, that is,ALTGX_RECO?FIG instance and ALTGX instance, we can get various groups bychanging settings of the devices without power off. These two blocks canaccomplish function of PCS (Physical Coding Sub-layer) and PMA (Physical MediumAttachment), however, with higher efficiency and reliability. (2) 1+1protection. In our design, two ALTGX IP cores are used to work in parallel,which named XAUI0 and XAUI1. The former works as the main channel while thelatter redundant channel. When XAUI0 is out of service for some reasons, XAUI1will start to work to keep the business. (3) RTL (Register Transfer Level)coding with Verilog HDL and simulation. Create the ALTGX_RECO?FIG instance andALTGX instance, enable dynamic reconfiguration in the ALTGXB Megafunction, thenconnect the ALTGX_RECO?FIG with the ALTGX instances. After RTL coding, thedesign was simulated on VCS simulator. The validated result indicates that thepackets are transferred efficiently. FPGA makes high-speed opticalcommunication system design simplified.

Design of a High Speed XAUI Based on Dynamic Reconfigurable Transceiver IP Core