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Test pattern NBS-3 is a microelectronic test vehicle designed by the National Bureau of Standards to evaluate the electronic materials used in discrete semiconductor devices and integrated circuits. Designed for fabrication on silicon wafers, the test pattern is an aid in better understanding integrated circuit fabrication technologies. The main pattern consists of four masks designated BASE, EMITTER, CONTACT, and METAL and contains 33 test structures such as sheet resistors, MOS capacitors, p-n junctions, bipolar and MOS transistors, and etch control and resolution structures. The pattern was designed primarily to aid in the evaluation of the relationship between resistivity and dopant density in both nand p-type silicon. This relation is needed in th'e design of silicon solid-state devices and in the analysis of various physical measurements. Other test structures are included for use as diagnostic tools to verify that proper fabrication procedures were followed. The remaining structures allow the exploration of new designs and measurement methods. The structures are arranged in a square pattern 200 mil (5.08 mm) on a side. A detailed layout of each test structure is presented including both a top view and a cross sectional view. A description of each structure is given and where applicable the formulas for evaluating such quantities as resistivity, dopant density, and sheet resistance are given. The fabrication of the test pattern is illustrated by an n-p-n transistor process and values obtained from various test structures are presented.

Microelectronic test pattern NBS-3 for evaluating the resistivity-dopant density relationship of silicon