Open AccessDesign of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization
Author(s) -
Ratna Chakrabarty,
Santanu Roy,
Tushar Shivam Pathak,
Nirabhra Mandal
Publication year - 2021
Publication title -
international journal of engineering
Language(s) - English
Resource type - Journals
eISSN - 1735-9244
pISSN - 1025-2495
DOI - 10.5829/ije.2021.34.12c.13
Subject(s) - comparator , quantum dot cellular automaton , computer science , logic gate , electronic engineering , cmos , digital electronics , realization (probability) , very large scale integration , cellular automaton , circuit design , 4 bit , electronic circuit , electrical engineering , algorithm , engineering , embedded system , mathematics , voltage , statistics
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